HPC Languages

June 29-July 2, 2013, in Lyon.

Set of keynotes: A dive into languages for high performance computing.

This scientific event is a collection of selected keynotes on high-performance computing languages and compiler approaches, with a special focus on the interactions of languages with compiler optimizations, runtime systems, and architecture specificities.

The evolution of the peak performances of processors has, for a long time, be due to the constant increase of clock frequency, the exploitation of instruction-level pipelining and parallelism, the introduction of hardware mechanisms for reordering instructions,  for hiding memory latencies, for predicting conditional branches, etc. For the every-day programmer, this performance increase has been felt, with no need to change programming paradigms. To bridge the gap between the high-level programming language and the low-level exploitation of processor architectures, compilation techniques (program transformations and optimizations) have been developed: loop unrolling, register allocation, instruction selection, peephole optimizations, optimizations beyond basic blocks, which are almost transparent for the user.

In the last years however, with the parallelism becoming mainstream, the pressure has became much stronger on the compiler, and even on the programming languages. Embedded processors for example, designed with a simpler architecture to reduce power consumption and size, with less hardware support for runtime optimizations, still offer good performances, for some classes of applications, but only thanks to optimizing compilers (e.g., exploitation of VLIW or vector operations) or even macros visible to the programmer (e.g., multi-media instructions). The development of GPUs (graphic processors) has led to considerable performance gains, again for some applications, but at the price of a loss of programming productivity: programming in CUDA or OpenCL is a task for specialists. Programming FPGAs is feasible only for experts and at low level. Multicores offer impressive computational power to a larger public but expose the user to the difficulty of parallel programming. Exascale computing, with difficult power and fault tolerance issues, leads to the same conclusion: it is not possible to exploit the peak performances of these machines for all applications (unlike “general purpose” processors) and by programming them almost transparently.

In other words, the development of these new hardware accelerators (FPGA, GPGPU, multicores), accessible to a larger public, but sometimes heterogeneous and always hard to program, has put a new pressure on programming languages and compilers to achieve the three¬†”P”: portability, programmability, performance. In this quest, a large number of research projects and high-performance computing (HPC) programming languages have been proposed, such as directives-based languages, PGAS (Partitioned Global Address Space) languages, streaming-like languages, actor-based languages, domain-specific languages (DSL), source-to-source compilers, high-level synthesis compilers, etc. It seems pertinent, in the context of this thematic quarter, to try to establish some links between these different approaches, to try to understand the compilation problems that each language or approach induces, the reasons for their design choices, the interactions with runtimes systems and architectures, etc.

This scientific event is organized as a set of keynotes by major actors of the field (see the program), including in particular talks on CAF (Coarray Fortran), UPC (Unified Parallel C), X10, Chapel, OpenACC & OpenHMPP, Lime, OmpSs, OpenStream, and some DSL approaches. The speakers will be given the time to go beyond a standard presentation, non only to present general ideas about their approaches or specific results, but also to discuss compilation challenges and unsolved problems encountered in the development of tools.

For all general questions concerning this event of keynotes, please contact Alain Darte at hpc-languages@ens-lyon.fr.

This event is also recognized by HIPEAC, the European Network of Excellence on High Performance and Embedded Architecture and Compilation.hipeac